Transistors are used in most portable electronic products such as cell phones, portable computers, voice recorders, etc., as well as in many larger electronic systems such as cars, planes, industrial control systems, etc. In the electronics industry, there have been constant challenges in trying to reduce the size of the devices in which the transistors are used and in the size of the transistors themselves.
One challenge of size reduction has been addressed by very large scale integration (VLSI) where there has been increasing integration of complementary metal oxide semiconductor field effect transistors (CMOS FETs).
However, reducing or scaling CMOS FETs has reached a critical junction. There are currently two main options for the next generation of transistor architectures: planar and three-dimensional architectures. A planar architecture requires the introduction of many new materials, e.g., new gate dielectrics, and new gate electrode materials. Further, structural changes are required such as elevated source/drain regions. Three-dimensional architectures have fewer disadvantages and have the advantages of increased drive current per unit area of silicon (Si) by increasing the channel width in the vertical third dimension, rather than only within the two-dimensional plane of the substrate.
One type of three dimensional architecture FET that allows increased device density is a “FinFET”. In a FinFET, the body of the transistor is formed with vertical structures, which individually resemble the dorsal “fin” of a fish. The gate of the FinFET has a vertical gate electrode with sidewall spacers and the source/drain fins are formed on either side of the sidewall spacers.
A FinFET has numerous advantages over a planar architecture FET including nearly ideal turn-off in sub-threshold voltages, giving lower off-currents and/or allowing lower threshold voltages, no loss to drain currents from body effects, no floating body effects (often associated with some Silicon on Insulator (SOI) FETs), higher current density, lower voltage operation, and reduced short channel degradation of threshold voltage and off-current. Thus, a FinFET provides better current control without requiring increased device size, and facilitates scaling of CMOS dimensions while maintaining acceptable performance.
However, it has been found that FinFETs are subject to various disadvantages. For example, deposition processes used to form the salicides, which electrically connects metal contacts to the silicon of the FinFET gate electrode and source/drain fins, only deposit metal on the top regions of these structures. This has been found to result in breaks in the gate electrode salicide leading to high-resistance gates and excessively high source/drain resistances.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.